/* SPDX-License-Identifier: GPL-2.0
 * csp.h - the chip operations file for IR
 *
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __IR_CSP_H__
#define __IR_CSP_H__
#include <mach/csp.h>
#include <mach/debug.h>

/* IR interrupt type */
#define K_IR_TO                 1
#define K_IR_F_ERR              2
#define K_IR_REPEAT             3
#define K_IR_FRAME              4
#define K_IR_START              5

/* IR protocol type */
#define K_IR_PROTOCOL_NEC                       0
#define K_IR_PROTOCOL_SONY_SIRC                 1
#define K_IR_PROTOCOL_RC5                       2
#define K_IR_PROTOCOL_RC6                       3

#define IR_SIRC_12		0
#define IR_SIRC_15		1
#define IR_SIRC_20		2
#define IR_SIRC_AUTO		3

#define K_IR_FRAME_GAP_NEC_MS_CNT		110
#define K_IR_FRAME_GAP_SIRC_MS_CNT		44
#define K_IR_FRAME_GAP_RC5_MS_CNT		110
#define K_IR_FRAME_GAP_RC6_MS_CNT		106

#define K_IR_BIT_PHASE_NEC_US_CNT		560
#define K_IR_BIT_PHASE_SIRC_US_CNT		600
#define K_IR_BIT_PHASE_RC5_US_CNT		889
#define K_IR_BIT_PHASE_RC6_US_CNT		444

#define K_IR_EFHOSC_FREQ			24000000	/* 24M */
#define K_IR_WORK_CLK_FREQ			100000		/* 100k */

/* IR register offset */
#define IR_CTL_OFF				(0x00000010)
#define IR_TIMEOUT_TH_OFF			(0x00000014)
#define IR_NOISE_TH_OFF				(0x00000018)
#define IR_INT_EN_OFF				(0x0000001C)
#define IR_INT_PD_OFF				(0x00000020)
#define IR_INT_CLR_OFF				(0x00000024)
#define IR_DATA_OFF				(0x00000028)

#ifndef CONFIG_ARCH_LOMBO_N7V1
#define IR_SADJ_OFF				(0x00000030)
#define IR_LADJ_OFF				(0x00000034)
#endif

/*
 * csp_ir_set_en - set IR enable
 * @en: 1, enable; 0, disable
 *
 */
void csp_ir_set_en(void *base, bool en);

/*
 * csp_ir_set_int_en - set IR interrupt enable
 * @t: select bit
 * @en: 1, interrupt enable; 0, interrupt disable
 *
 */
void csp_ir_set_int_en(void *base, int t, bool en);

/*
 * csp_ir_int_clr - clear IR interrupt pending
 * @t: select bit
 *
 * the bit of interrupt is writing 1 clears pending
 */
void csp_ir_int_clr(void *base, int t);

/*
 * csp_ir_set_protocol - set IR interrupt enable
 * @t: 0, NEC; 1, SIRC; 2, RC5; 3, RC6
 * @en: 1, interrupt enable; 0, interrupt disable
 *
 */
void csp_ir_set_protocol(void *base, int p);

/*
 * csp_ir_set_sirc_ext - SIRC protocol select
 * @ext: 0, 12bit frame; 1, 15bit frame; 2, 20bit frame; 3, auto-adjust frame
 *
 */
void csp_ir_set_sirc_ext(void *base, u32 ext);

/*
 * csp_ir_set_clk_div - set IR clock diver
 * @div: frequency division
 *
 */
void csp_ir_set_clk_div(void *base, u32 div);

/*
 * csp_ir_set_timeout_th - set IR timeout threshold
 * @th: timeout threshold
 *
 */
void csp_ir_set_timeout_th(void *base, u32 th);

/*
 * csp_ir_set_noise_th - set IR noise threshold
 * @th: timeout threshold
 *
 */
void csp_ir_set_noise_th(void *base, u32 th);

/*
 * csp_ir_get_data - get IR received data
 * @param: none
 *
 * return: IR frame
 */
u32 csp_ir_get_data(void *base);

#ifndef CONFIG_ARCH_LOMBO_N7V1
/*
 * csp_ir_set_short_adj - set IR short adjustment
 * @adj: adjustment
 *
 */
void csp_ir_set_short_adj(void *base, u32 adj);

/*
 * csp_ir_set_long_adj - set IR long adjustment
 * @adj: adjustment
 *
 */
void csp_ir_set_long_adj(void *base, u32 adj);
#endif

#ifdef CONFIG_ARCH_LOMBO_N9V3

/* clock source select in ir module domain */
enum ir_clk_src {
	RCOSC = 0,	/* 16M */
	RTCCLK = 1,	/* 32k */
};

/* set power key wake up function enable */
void csp_ir_set_wk_en(void *base, u32 en);

/* if set 1, it will reset all registers and state machine */
void csp_ir_set_ir_rstn(void *base, u32 reset);

/* set ir module clock source */
void csp_ir_set_clk_src(void *base, enum ir_clk_src src);

void csp_ir_set_wake_expect_data(void *base, u32 exp_data);

u32 csp_ir_get_wake_expect_data(void *base);

void csp_ir_set_wake_data_mask(void *base, u32 wk_mask);

u32 csp_ir_get_wake_data_mask(void *base);

#endif /* CONFIG_ARCH_LOMBO_N9V3 */

#endif
